1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory system exchanging signals through a channel and an operating method thereof.
2. Description of the Related Art
Semiconductor devices including a double data rate synchronous DRAM (DDR SDRAM) are being developed in various directions in order to meet users' demands, and development of package technologies of a semiconductor device is also in progress. Recently, a multi-chip package (MCP) has been proposed as one of the package technologies. According to the multi-chip package, a plurality of semiconductor chips are packaged to configure a single chip, wherein it is possible to increase a memory capacity with a storage function of the memory chips or to improve a desired performance with various non-storage function of the semiconductor chips. Multi-chip packages may be classified into a single layer-type multi-chip package and a multi-layer-type multi chip package according to the configuration thereof. In the single layer-type multi-chip package, a plurality of semiconductor chips are disposed side by side on a plane. In the multi-layer-type multi-chip package, a plurality of semiconductor chips that are stacked perpendicularly.
When a plurality of semiconductor chips are implemented as a multi-layer-type multi-chip package, the input/output terminals of each semiconductor chip were implemented by wire bonding in the past, However, when the wire bonding is used, a chip implemented thereby may have flaws in a high-speed operation and noises. Recently, a chip-on-chip package technology has been used in place of the wire bonding.
According to the chip-on-chip package technology, each of the semiconductor chips has bump pads whose disposition of all of the semiconductor chips is identical, and thus the semiconductor chips may be perpendicularly stacked and connected to each other with the bumps of same disposition. When such a chip-on-chip package technology is used, it is possible to achieve a high-speed operation, and also to reduce power consumption. In addition, the chip-on-chip package technology may minimize the entire area of a multi-chip package, so that the chip-on-chip package technology is one of recently highlighted technologies.
FIG. 1 is a block view illustrating a conventional semiconductor memory system.
Referring to FIG. 1, a semiconductor memory system includes a memory control device 110 and a plurality of memory devices 121 to 124.
The memory control device 110 transfers/receives various signals with the plurality of memory devices 121 to 124, wherein the signals may include, for example, a command, an address, data, and the like. The memory control device 110 has channels to transfer/receive such signals. Hereinafter, for convenience of description, it is assumed as an example that the memory control device 110 has a first channel 111 and a second channel 112, each of which has 2n number of transmission lines (here, n is a natural number). In addition, a first memory device 121 and a second memory device 122 are controlled by the memory control device 110, and each of the first and second memory devices is connected to n number of transmission lines included in the first channel 111. A third memory device 123 and a fourth memory device 124 are also controlled by the memory control device 110, and each of the third and fourth memory devices is connected to n number of transmission lines included in the second channel 112.
Meanwhile, in response to an input for desired operation from a user to the memory control device 110, the memory control device 110 controls the plurality of memory devices 121 to 124. In this case, the memory control device 110 determines a signal transfer bandwidth and selects and activates appropriate channel. That is to say, according to the control of the memory control device 110, it can be set to use both first and second channels 111 and 112, or to use only any one of the first and second channels 111 and 112. In addition, the signal transfer bandwidth of an activated channel can be set to “n” or “2n”.
However, when the signal transfer bandwidth of each channel to is set to “n”, that is to say, when only any one memory device of the first and second memory devices 121 and 122 is used, and only one memory device of the third and fourth memory devices 123 and 124 is used, the utilization efficiency of memory devices to an area occupied by the first to fourth memory devices 121 to 124 drops to 50% or less.
FIG. 2 is a block view illustrating another example of a conventional semiconductor memory system.
Referring to FIG. 2, a semiconductor memory system includes a memory control device 210, and a plurality of memory devices 220. The semiconductor memory system of FIG. 2 is different from that of FIG. 1 in the number of the plurality of memory devices 220. That is to say, FIG. 2 illustrates a case where two memory devices, i.e. a first memory device 221 and a second memory device 222, are included. Here, the first memory device 221 is connected to 2n number of transmission lines included in a first channel 211, and the second memory device 222 is connected to 2n number of transmission lines included in a second channel 212.
Similarly to FIG. 1, the memory control device 210 determines a signal transfer bandwidth, and selects and activates one of the first and second channels 211 and 212 according to an input for desired operation from a user. However, when the signal transfer bandwidth of each channel is set to “n”, only “n” number of transmission lines among 2n number of transmission lines connected to the first memory device 221 are used, and only “n” number of transmission lines among 2n number of transmission lines connected to the second memory device 222 are used, the first and second memory devices 221 and 22 must be both activated, so that the power consumption of memory devices to a signal transfer bandwidth may increase.